This invention relates in general to time measurement circuits, and more particularly to circuits for measuring elapsed time between two asynchronous electric pulses.
The manufacture and use of electronic circuits requires that parameters such as switching speeds and gate delay times are measured accurately. Commonly, time measurement circuits produce an output that is proportional to the amount of time that passes between two events. Usually, each of these events are marked by a transition from a logic low state to a logic high state or vice-versa. Most often it is this transition, or pulse edge, which is used to trigger the time measurement circuit. The term "pulse edge" as used hereinafter is intended to encompass any transition between a logic low state to a logic high state, or vice-versa. Most logic devices recognize either a rising or falling edge of a waveform and rarely require both a rising and falling edge. Depending on the type of logic devices used, the term pulse edge can be taken to mean a rising edge, a falling edge, or a combination of the two.
A simple way of measuring time between two asynchronous pulse edges, or data edges, is to provide a clock, and count the number of clock edges which occur between the data edges. This simple method results in a crude time measurement which is limited in accuracy to the speed of the clock used. Since typical clock periods are in the order of 1 nanosecond, this method clearly cannot work for picosecond measurement accuracy.
To improve accuracy, elapsed time between each data edge, and the next clock edge must be measured. This can be done by providing a ramp circuit which has an output signal which increases linearly with time. One of the data edges is used to start the ramp circuit, while a subsequent clock edge is used to stop the ramp circuit. One such ramp circuit must be used for each of the two data edges. The ramp circuit has an analog output which is proportional to the elapsed time between the data edge, and the next clock edge. This analog data can be converted to digital data, and added to the count of clock pulses described hereinbefore. It should be noted that ramp circuits will often take several hundred or thousands of times longer to make a measurement than the actual event took. For example, if the elapsed time between the data edge and the next clock edge were 0.5 nanoseconds, a typical ramp circuit may take 500 nanoseconds to measure the elapsed time. Also, physical size of the ramp circuit is a function of the length of time which must be measured. Therefore, it is useful to minimize the time which must be measured by the ramp circuit.
In order to select the next clock edge which occurs after the data edge, a D-type flip flop is used having the data edge coupled to a data (D) input, and the clock edge coupled to a clock input. Using this arrangement, once the data edge appears on the D input, the output (Q) of the D flip flop will switch after the next clock edge comes to the clock input. Thus the Q output of the D flip flop will go high when the first clock edge after the data edge occurs. The output of the D flip flop is then coupled to the ramp circuit and is used to stop the ramp circuit.
While this basic circuit works well in theory, practical problems occur when the clock edge and data edge occur too close together. When the clock edge and data edge are so close together as to violate setup or hold time of the flip flop, the output of the flip flop will be uncertain. This uncertain output is also called a metastable state. The metastable output may or may not trigger the ramp circuit to stop. Also, propagation delay of the D-type flip flop is unknown in a metastable state, so accurate time measurement is impossible. The metastable state will eventually drift to either a logic high or logic low state, but this may take several clock periods to occur.
Circuits have been devised to reduce the occurrence of a metastable state. Commonly, a series of three or four D flip flops are used in place of the single D flip flop described above. By using three flip flops, the probability that the metastable state would reach a logic high or logic low within a clock period was greatly improved. A significant probability remained that the metastable state will be transferred through the series of flip flops, however, and eventually reach the time measurement circuit. This is increasingly probable when short clock periods were used.
To compensate for the possibility of a metastable state, several thousand measurements were usually taken, and averaged to improve accuracy. Although this method allowed the erroneous data caused by the metastable state to be averaged out, it obviously took much longer than a single measurement. Multiple measurements could actually take several milliseconds or even seconds to get an accurate measurement of an event which took only a few picoseconds. This additional time is unacceptable when many thousands or millions of measurements must be taken, as is the case for testing semiconductor integrated circuits. Also, some transient events cannot be repeated, and thus repeated measurements cannot be taken. In these cases, errors caused by the metastable state make accurate time measurement impossible.
Accordingly, it is an object of the present invention to provide a time measurement circuit with improved accuracy.
Another object of the present invention is to provide a method for measuring elapsed time in the order of a few picoseconds.
Another object of the present invention is to provide a time measurement system which reduces the time which a ramp circuit is required to measure.
Another object of the present invention is to provide a method for measuring elapsed time so accurately that multiple measurements are not necessary.
A further object of the present invention is to provide a time measurement system which removes errors caused by propagation delay change of flip flops operating in a metastable state.